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features ? pfc, ballast control and half-bridge driver in one ic ? critical conduction mode boost type pfc ? no pfc current sense resistor required ? programmable preheat frequency ? programmable preheat time ? programmable run frequency ? programmable over-current protection ? programmable end-of-life protection data sheet no. pd60198 reve ir2166(s) & (pbf) pfc & ballast control ic ir2166 application diagram ? programmable dead time ? internal ignition ramp ? internal fault counter ? dc bus under-voltage reset ? shutdown pin with hysteresis ? internal 15.6v zener clamp diode on vcc ? micropower startup (150 a) ? latch immunity and esd protection ? 16-lead pdip also available lead-free description the ir2166 is a fully integrated, fully protected 600v ballast control ic designed to drive all types of fluorescent lamps. pfc circuitry operates in critical conduction mode and provides for high pf, low thd and dc bus regulation. the ir2166 features in- clude programmable preheat and run frequencies, programmable preheat time, pro- grammable dead-time, programmable over-current protection, and programmable end- of-life protection. comprehensive protection features such as protection from failure of a lamp to strike, filament failures, end-of-life protection, dc bus undervoltage reset as well as an automatic restart function, have been included in the design. the ir2166 is available in both 16-lead pdip and 16-lead (narrow body) soic packages. www.irf.com 1 packages *please note that this data sheet contains advanced information that could change before the product is released to production. 16-lead soic (narrow body) 16-lead pdip also available lead-free + rectified ac line - rectified ac line r bus 15 14 13 12 11 ir2166 com vcc vb vs ho 1 2 3 cph pfc vbus 4 5 7 rt ct rph 6 7 8 zx comp 10 cs lo 9 sd/eol 16 d bus d cp2 m3 + c vdc r vdc c t r t r ph c ph c comp c bus r ghs m1 r gpfc l res c block c cs r cs r gls m2 r 4 r 3 r supply d boot c boot c snub d cp1 r 2 c vcc2 c vcc1 + c res c sd1 c sd2 r 5 r 6 r 7 r 8 d 1 d 2 d 3 r 1 dz comp c eol
ir2166 & (pbf) 2 www.irf.com absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com, all currents are defined positive into any lead. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. note 1: this ic contains a zener clamp structure between the chip v cc and com which has a nominal breakdown voltage of 15.6v. please note that this supply pin should not be driven by a dc, low impedance power source greater than the v clamp specified in the electrical characteristics section. symbol definition min. max. units v b high side floating supply voltage -0.3 625 v s high side floating supply offset voltage v b - 25 v b + 0.3 v ho high side floating output voltage v s - 0.3 v b + 0.3 v lo low side output voltage -0.3 v cc + 0.3 v pfc pfc gate driver output voltage -0.3 v cc + 0.3 i omax maximum allowable output current (ho, lo, pfc) -500 500 due to external power transistor miller effect v bus v bus pin voltage -0.3 v cc + 0.3 v ct ct pin voltage -0.3 v cc + 0.3 i cph cph pin current -5 5 i rph rph pin current -5 5 v rph rph pin voltage -0.3 v cc + 0.3 v i rt rt pin current -5 5 ma v rt rt pin voltage -0.3 v cc + 0.3 v cs current sense pin voltage -0.3 5.5 i cs current sense pin current -5 5 i sd/eol shutdown pin current -5 5 i cc supply current (note 1) -20 20 i zx pfc inductor current, zero crossing detection input current -5 5 i comp pfc error compensation current -5 5 dv/dt allowable offset voltage slew rate -50 50 v/ns p d package power dissipation @ t a +25 c (16-pin pdip) 1.80 p d = (t jmax -t a )/rth ja (16-pin soic) 1.40 rth ja thermal resistance, junction to ambient (16-pin pdip) 70 (16-pin soic) 86 t j junction temperature -55 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) 300 v ma ma v ma v w o c/w o c
ir2166 & (pbf) www.irf.com 3 note 2: enough current should be supplied into the v cc lead to keep the internal 15.6v zener clamp diode on this lead regulating its voltage, v clamp . recommended operating conditions for proper operation the device should be used within the recommended conditions. symbol definition min. max. units v bs high side floating supply voltage v cc - 0.7 v clamp v s steady state high side floating supply offset voltage -1 600 v cc supply voltage v ccuv+ v clamp i cc supply current note 2 10 ma c t ct lead capacitance 220 ? pf i sd/eol end-of-life lead current -1 1 i cs current sense lead current -1 1 i zx zero crossing detection pin current -1 1 t j junction temperature -25 125 o c v ma electrical characteristics v cc = v bs = v bias = 14v +/- 0.25v, v bus = open, r t = 39.0k ? , r ph = 100k ? , c t = 470 pf, v cph = 0.0v, v sd = 0.0v, v comp = 0.0v, v cs = 0.0v, c lo = c ho = 1000pf, t a = 25 o c unless otherwise specified. symbol definition min. typ. max. units test conditions supply characteristics v ccuv+ v cc supply undervoltage positive going 10.0 11.5 12.5 v cc rising from 0v threshold v ccuv- v cc supply undervoltage negative going 8.5 9.5 10.7 v cc falling from 14v threshold v uvhys v cc supply undervoltage lockout hysteresis 1.5 2.0 3.0 i qccuv uvlo mode quiescent current 145 170 290 av cc = 8v i qcc quiescent v cc supply current 2.3 4.0 ma ct connected to com vcc =14v v clamp v cc zener clamp voltage 14.3 15.6 17 v i cc = 10ma i qbs0 quiescent v bs supply current -1 0 5 v ho = v s (c t = 0v) i qbs1 quiescent v bs supply current 5 30 70 v ho = v b (c t = 14v) v bsmin minimum required v bs voltage for proper 2.5 v ho functionality i lk offset supply leakage current 50 a v b = v s = 600v a floating supply characteristics v
ir2166 & (pbf) 4 www.irf.com electrical characteristics cont. v cc = v bs = v bias = 14v +/- 0.25v, v bus = open, r t = 39.0k ? , r ph = 100k ? , c t = 470 pf, v cph = 0.0v, v sd = 0.0v, v comp = 0.0v, v cs = 0.0v, c lo = c ho = 1000pf, t a = 25 o c unless otherwise specified. symbol definition min. typ. max. units test conditions i comp error amplifier output current sourcing 5 35 55 v cph = 14v source v bus = 3.5v i comp error amplifier output current sinking -62 -30 -12 v cph = 14v sink v bus = 4.5v v compoh error amplifier output voltage swing 10.5 13.5 14.5 v bus = 3.0v (high state) v compol error amplifier output voltage swing 0.25 4 v bus = 5.0v (low state) pfc error amplifier characteristics v a v busov overvoltage comparator threshold 3.8 4.3 4.7 v v comp = 4.0v v busov overvoltage comparator hysterisis 150 300 400 mv v comp = 4v hys v vbus vbus internal reference voltage 3.7 4.0 4.2 v v comp = 4v reg pfc dc bus regulation v zx zx pin comparator threshold voltage 1.1 1.65 2 v v comp = 4v v zxhys zx pin comparator hysterisis 75 300 800 mv v comp = 4v v zxclamp zx pin clamp voltage (high state) 6.3 7.5 9.1 v i zx = 5ma pfc zero current detector rph characteristics i rphlk open circuit rph pin leakage current 0.1 a v rphflt fault-mode rph pin voltage 0 mv sd > 5.0v or cs > 1.3v pfc watch-dog t wd watch-dog pulse interval 90 400 824 s zx = 0v, v comp> =2v ballast control preheat characteristics i cph cph pin charging current 2.6 3.2 4.6 a v cph =5v,ct=0v, v bus =0v v cphflt fault-mode cph pin voltage 0 mv sd > 5.0v or cs > 1.3v ballast control oscillator characteristics f osc oscillator frequency 39 42 50 run mode 73 78 84 preheat mode d oscillator duty cycle 50 % v ct+ upper c t ramp voltage threshold 6.8 8.4 10.7 v ct- lower c t ramp voltage threshold 1.8 4.6 5.6 v ctflt fault-mode c t lead voltage 0 sd > 5.0v or cs > 1.3v t dlo lo output deadtime 0.7 1.0 1.5 t dho ho output deadtime 0.7 1.0 1.5 v v cc = 14v usec ct = 470pf khz
ir2166 & (pbf) www.irf.com 5 electrical characteristics cont. v cc = v bs = v bias = 14v +/- 0.25v, v bus = open, r t = 39.0k ? , r ph = 100k ? , c t = 470 pf, v cph = 0.0v, v sd = 0.0v, v comp = 0.0v v cs = 0.0v, c lo = c ho = 1000pf, t a = 25 o c unless otherwise specified. symbol definition min. typ. max. units test conditions rt characteristics i rtlk open circuit rt pin leakage current 0.1 a ct = 10v v rtflt fault-mode rt pin voltage 0 mv sd > 5.0v or cs > 1.3v v ol low-level output voltage 0 100 io = 0 v oh high-level output voltage 0 100 v bias - vo, io = 0 tr turn-on rise time 110 210 tf turn-off fall time 55 160 i0+ ho, lo, pfc source current 300 i0- ho, lo, pfc sink current 400 gate driver output characteristics (ho, lo and pfc pins) mv nsec c ho = c lo = c pfc = 1nf ma v sdth+ rising shutdown pin reset threshold voltage 4.5 5.2 5.6 v v sdhys shutdown pin 5.0v threshold hysteresis 100 150 350 mv v sdeol+ rising shutdown pin end-of-life threshold volt. 2.4 3.0 3.6 v sdeol - falling shutdown pin end-of-life threshold volt. 0.7 1.0 1.6 v csth+ over-current sense threshold voltage 0.91 1.2 1.3 v cph >7.5v #fault - number of sequential over-current fault 25 75 90 cycles v cph >7.5v, cycles cycles before ic shuts down cs > 1.3v v busuv- the vbus threshold below which the ic 2.6 3.0 3.3 shuts down v cph cph pin end-of-life enable threshold 10.3 12 13.2 protection circuitry characteristics v v cph >12v v
ir2166 & (pbf) 6 www.irf.com block diagram pfc comp zx 7.6v 1.0v q s r2 q r1 q s rq vcc rt cph vcc ct rph com r v th r 3ua r driver logic comp 1 schmitt 1 sd/eol r r rdt 3.0k 40k s1 s2 s3 s4 q t rq s6 q s r2 q r1 vbus vb ho vs lo cs high- side driver low- side driver 1.3v comp 3 10 13 3 5 4 2 1 9 14 16 15 11 8 6 7 under- voltage detect watch dog timer 12 soft start over-voltage protection 4.3v fault counter 2.0v 1.0m 5.2v 1v 3v cph>12v 4.0v 3.0v q s rq under-voltage reset vcc fault logic 7.6v cph>12v gain ota1
ir2166 & (pbf) www.irf.com 7 state diagram vcc < 9.5v (vcc fault or power down) or sd/eol > 5.0v (lamp fault or lamp removal) uvlo mode 1 / 2 -bridge off i qcc ? 400 a cph = 0v ct = 0v (oscillator off) preheat mode 1 / 2 -bridge oscillating @ f ph rph // rt cph charging @ i cph = 5 a pfc enabled (high gain) cs enabled fault counter enabled vcc > 11.5v (uv+) and sd/eol < 5.0v power turned on fault mode fault latch set 1 / 2 -bridge off i qcc ? 180 a cph = 0v vcc = 15.6v ct = 0v (oscillator off) cs > 1.3v for 25 cycles (failure to strike lamp) sd/eol > 5.0v (lamp removal) or vcc < 9.5v (uv-) (power turned off) cph > (vcc - 4v) (end of preheat mode) ignition ramp mode rph > open f ph ramps to f run cph charging cph > (vcc - 2v) cs > 1.3v (lamp fault) or sd/eol<1.0v or sd/eol>3.0v (end-of-life) run mode rph = open 1/2-bridge oscillating @f run eol thresholds enabled pfc = low gain mode vbus uv threshold enabled fault counter disabled vbus<3.0v cs > 1.3v for 25 cycles discharge vcc to uvlo-
ir2166 & (pbf) 8 www.irf.com lead assignments & definitions pin # symbol description 1 3 7 6 5 4 2 vbus zx comp cph ct rph rt logic & low-side gate driver supply dc bus sensing input minimum frequency timing resistor preheat frequency timing resistor oscillator timing capacitor preheat timing capacitor pfc error amplifier compensation pfc pfc zero-crossing detection 8 9 11 15 14 13 12 10 sd/eol vs vb vcc com lo cs pfc gate driver output ic power & signal ground shut-down/end of life sensing circuit current sensing input low-side gate driver output high voltage floating return high-side gate driver output ho high-side gate driver floating supply 16 15 14 13 12 11 ir2166 com vcc vb vs ho 1 2 3 rt cph vbus 4 5 7 rph comp ct 6 7 8 pfc zx 10 cs lo 9 sd/eol 16
ir2166 & (pbf) www.irf.com 9 vcc ho lo uvlo+ 15.6v ballast timing diagrams normal operation uvlo- cph cs ph ign run uvlo uvlo 1.3v over-current threshold freq 7.5v vcc f ph f run rt ct lo cs ho rph rt ct lo cs ho rph rt ct lo cs ho rph
ir2166 & (pbf) 10 www.irf.com vcc ho lo uvlo+ 15.6v ballast timing diagrams fault condition uvlo- cph cs ph ign run uvlo uvlo 1.3v freq 7.5v vcc f p h f run fault ph ign sd > 5.1v sd rt ct lo cs ho rph rt ct lo cs ho rph rt ct lo cs ho rph
ir2166 & (pbf) www.irf.com 11 1000 10000 100000 1000000 5 25456585 rt(k ? ) frequency (khz) graph 2. ct vs dead time graph 3: ct+, ct- vs temp graph 4: frequency vs rt graph 1. vccuv+, vccuv- vs temp 0 1 2 3 4 5 6 7 8 9 -25 0 25 50 75 100 125 temperature (c) ct (v) ct+ ct- 0 2 4 6 8 10 12 14 -25 0 25 50 75 100 125 temperature (c) vcc (v) uvlo+ uvlo- 0 200 400 600 800 1000 1200 1400 1600 00.5 11.522.53 deadtime( s) ct (pf)
ir2166 & (pbf) 12 www.irf.com 0 1 2 3 4 5 6 7 8 40 80 120 160 200 frequency (khz) icc (ma) -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 03691215 vcph (v) icph (ma) 0 10 20 30 40 50 -25 0 25 50 75 100 125 temperature (c) ilk ( a) graph 5: icc vs frequency graph 6: icph vs vcph graph 7. ilk vs temp graph 8: zx+, zx- vs temp 0 0.5 1 1.5 2 2.5 -250255075100125 temperature (c) zx threshold & hys.(v ) zx + zx - hys
ir2166 & (pbf) www.irf.com 13 275 285 295 305 315 325 -25 0 25 50 75 100 125 temperature (c) izx(zxinput bias) ( a) 6 6.5 7 7.5 8 8.5 9 -25 0 25 50 75 100 125 temperature (c) graph 9: izx (zx input bias) vs temp graph 10: vzx (zx clamp voltage) vs temp 3 3.5 4 4.5 5 -25 0 25 50 75 100 125 temperature (c) 3 3.5 4 4.5 5 -25 0 25 50 75 100 125 temperature (c) vbus+ vbus- graph 11: vbus sense thresh vs temp graph 12: vbus+, vbus- vs temp
ir2166 & (pbf) 14 www.irf.com 53 55 57 59 61 63 -25 0 25 50 75 100 125 temperature (c) freq(khz) 1.5 1.7 1.9 2.1 2.3 2.5 -25 0 25 50 75 100 125 temperature (c) t dead ( s) t dead ho t dead lo graph 13: pfc trise, tfall vs temp graph 14: frequency vs temp graph 15: t dead ho , t dead lo vs temp 0 25 50 75 100 125 150 175 200 -25 0 25 50 75 100 125 temperature (c) t rise, t fall (ns) t rise t fall graph 16: t rise , t fall vs temp 0 25 50 75 100 125 150 -25 0 25 50 75 100 125 temperature (c) pfc trise, tfall (ns) trise tfall
ir2166 & (pbf) www.irf.com 15 graph 17: cs pulses vs temp 0 1 2 3 4 5 -25 0 25 50 75 100 125 temperature (c) cs threshold (v) graph 18: cs threshold vs temp graph 20: sd+, sd- vs temp 0 0.5 1 1.5 2 2.5 3 3.5 -25 0 25 50 75 100 125 temperature (c) v sd/eol (v) graph 19: eol+,eol- vs temp eol+ eol- 4 4.5 5 5.5 6 -25 0 25 50 75 100 125 temperature (c) v sd/eol (v) sd+ sd- 0 10 20 30 40 50 -25 0 25 50 75 100 125 temperature (c) # cs pulses
ir2166 & (pbf) 16 www.irf.com 10 11 12 13 14 15 -25 0 25 50 75 100 125 temperature (c) vcph(eol/run) threshold (v ) graph 21: vcph (eol/run) threshold vs temp 0 2 4 6 8 10 12 14 16 0 5 10 15 20 pfc on time ( s) v comp (v) graph 23: vcomp vs pfc on time -10 0 10 20 30 40 50 60 70 80 90 03691215 v bs (v ) i qbs ( a) 0 0.5 1 1.5 2 2.5 3 8 9 10 11 12 13 v cc (v) i qcc (ma) graph 22: i qcc vs v cc uvlo hysteresis graph 24: i qbs (1) vs v cc vs temp
ir2166 & (pbf) www.irf.com 17 0 4 8 12 16 20 0 5 10 15 20 v cc (v) i qcc (ma) -25 25 75 125 graph 25. i qcc vs v cc vs temp 0 0.05 0.1 0.15 0.2 0.25 0.3 0 3 6 9 12 15 v cc (v) i qcc (ma) -25 25 75 125 graph 27. i qcc vs v cc vs temp micro p ower startu p mode 0 4 8 12 16 20 15 15.5 16 16.5 v cc (v) i qcc (ma) -25 25 75 125 graph 26. i qcc vs v cc vs temp internal zener diode curve graph 28: i qcc vs v cc vs temp v ccuv + 0 0.5 1 1.5 2 2.5 10 10.5 11 11.5 12 12.5 13 v cc (v) -25 25 75 125
ir2166 & (pbf) 18 www.irf.com 0 0.5 1 1.5 2 2.5 3 8.5 9 9.5 10 10.5 v cc (v) i qcc ( a) -25 25 75 125 graph 29: i qcc vs v cc vs temp v ccuv -
ir2166 & (pbf) www.irf.com 19 ir2166 lo com vb vs ho v bus (+) v bus (-) vcc d boot c boot 16 15 14 13 12 11 m2 m1 c vcc r supply d cp1 d cp2 half-bridge output r cs c snub i. ballast section functional description under-voltage lock-out mode (uvlo) the under-voltage lock-out mode (uvlo) is defined as the state the ic is in when vcc is below the turn-on threshold of the ic. to identify the different modes of the ic, refer to the state diagram shown on page 7 of this document. the ir2166 undervoltage lock-out is designed to maintain an ultra low supply current of less than 400ua, and to guarantee the ic is fully functional before the high and low side output drivers are activated. figure 1 shows an efficient supply voltage using the start-up current of the ir2166 together with a charge pump from the ballast output stage (r supply , c vcc , d cp1 and d cp2 ). figure 1, start-up and supply circuitry. the start-up capacitor (cvcc) is charged by current through supply resistor (rsupply) minus the start-up current drawn by the ic. this resistor is chosen to set the line input voltage turn-on threshold for the ballast . once the capacitor voltage on vcc reaches the start-up threshold, and the sd pin is below 5.0 volts, the ic turns on and ho and lo begin to oscillate. the capacitor begins to discharge due to the increase in ic operating current (figure 2). discharge time internal vcc zener clamp voltage vhyst v uvlo+ v uvlo- charge pump output t v c1 r supply & c vcc time constant c vcc discharge figure 2, supply capacitor (c vcc ) voltage. during the discharge cycle, the rectified current from the charge pump charges the capacitor above the ic turnoff threshold. the charge pump and the internal 15.6v zener clamp of the ic take over as the supply voltage. the start-up capacitor and snubber capacitor must be selected such that enough supply current is available over all ballast operating conditions. a bootstrap diode (dboot) and supply capacitor (cboot) comprise the supply voltage for the high side driver circuitry. to guarantee that the high-side supply is charged up before the first pulse on pin ho, the first pulse from the output drivers comes from the lo pin. during under-voltage lockout mode, the high- and low-side driver outputs ho and lo are both low, pin ct is connected internally to com to disable the oscillator, and pin cph is connected internally to com for resetting the preheat time. preheat mode (ph) the preheat mode is defined as the state the ic is in when the lamp filaments are being heated to their correct emission temperature. this is necessary for maximizing lamp life and reducing the required ignition voltage. the ir2166 enters preheat mode when vcc exceeds the uvlo positive-going threshold. ho and lo begin to
ir2166 & (pbf) 20 www.irf.com 4 3 3ua 5 2 cph ct rph rt 11 12 com lo m2 r cs osc 16 ho m1 15 vs c cph c t half- bridge output i load (+) v bus (-) load return half- bridge driver ir2166 1.3v s1 s4 comp 4 10 13 vcc cs r1 c cs s3 fault logic v bus r t r ph oscillate at the preheat frequency with 50% duty cycle and with a dead-time which is set by the value of the external timing capacitor, ct, and internal deadtime resistor, rdt. pin cph is disconnected from com and an internal 3 a current source (figure 3) figure 3, preheat circuitry. charges the external preheat timing capacitor on cph linearly. the over-current protection on pin cs is disabled during preheat. the preheat frequency is determined by the parallel combination of resistors rt and rph, together with timing capacitor ct. ct charges and discharges between 1/3 and 3/5 of vcc (see timing diagram, page 9). ct is charged exponentially through the parallel combination of rt and rph connected internally to vcc through mosfet s1. the charge time of ct from 1/3 to 3/5 vcc is the on-time of the respective output gate driver, ho or lo. once ct exceeds 3/5 vcc, mosfet s1 is turned off, disconnecting rt and rph from vcc. ct is then discharged exponentially through an internal resistor, rdt, through mosfet s3 to com. the discharge time of ct from 3/5 to 1/3 vcc is the dead-time (both off) of the output gate drivers, ho and lo. the selected value of ct together with rdt therefore program the desired dead-time (see design equations, page 26, equations 1 and 2). once ct discharges below 1/3 vcc, mosfet s3 is turned off, disconnecting rdt from com, and mosfet s1 is turned on, connecting rt and rph again to vcc. the frequency remains at the preheat frequency until the voltage on pin cph exceeds 10v and the ic enters ignition mode. during the preheat mode, the over-current protection together with the fault counter are enabled. the peak ignition current must not exceed the maximum allowable current ratings of the output stage mosfets. should this voltage exceed the internal threshold of 1.3v, the internal fault counter begins counting the sequential over- current faults (see timing diagram). if the number of over-current faults exceed 25, the ic will enter fault mode and gate driver outputs ho, lo and pfc will be latched low. figure 4, ignition circuitry. 4 3 3ua 5 2 cph ct rph rt 11 12 com lo m2 rcs osc. 16 ho m1 15 vs r t c cph half- bridge output i load v bus (+) v bus (-) load return half- bridge driver ir2166 s4 r ph c t
ir2166 & (pbf) www.irf.com 21 ignition mode (ign) the ignition mode is defined as the state the ic is in when a high voltage is being established across the lamp necessary for igniting the lamp. the ir2166 enters ignition mode when the voltage on pin cph exceeds 10v. pin cph is connected internally to the gate of a p-channel mosfet (s4) (see figure 4) that connects pin rph with pin rt. as pin cph exceeds 10v, the gate-to-source voltage of mosfet s4 begins to fall below the turn-on threshold of s4. as pin cph continues to ramp towards vcc, switch s4 turns off slowly. this results in resistor rph being disconnected smoothly from resistor rt, which causes the operating frequency to ramp smoothly from the preheat frequency, through the ignition frequency, to the final run frequency. the over-current threshold on pin cs will protect the ballast against a non-strike or open-filament lamp fault condition. the voltage on pin cs is defined by the lower half-bridge mosfet current flowing through the external current sensing resistor rcs. the resistor rcs therefore programs the maximum allowable peak ignition current (and therefore peak ignition voltage) of the ballast output stage. if the number of over current pulses exceed 25, the ic will enter fault mode and gate driver outputs ho, lo and pfc will be latched low. run mode (run) once the lamp has successfully ignited, the ballast enters run mode. the run mode is defined as the state the ic is in when the lamp arc is established and the lamp is being driven to a given power level. the run mode oscillating frequency is determined by the timing resistor rt and timing capacitor ct (see design equations, page 26, equations 3 and 4). should hard-switching occur at the half-bridge at any time due to an open-filament or lamp removal, the voltage across the current sensing resistor, rcs, will exceed the internal threshold of 1.3 volts and the ic will enter fault mode and gate driver outputs ho, lo and pfc will be latched low. dc bus under-voltage reset should the dc bus decrease too low during a brownout line condition or overload condition, the resonant output stage to the lamp can shift near or below resonance. this can produce hard-switching at the half-bridge which can damage the half-bridge switches or, the dc bus can decrease too far and the lamp can extinguish. to protect against this, the vbus pin includes a 3.0v under-voltage threshold. should the voltage at the vbus pin decrease below 3.0v, vcc will be discharged to the uvlo- threshold and all gate driver outputs will be latched low. for proper ballast design, the designer should design the pfc section such that the dc bus does not drop until the ac line input voltage falls below the rated input voltage of the ballast (see pfc section). when correctly designed, the voltage measured at the vbus pin will decrease below the internal 3.0v threshold and the ballast will turn off cleanly. the pull-up resistor to vcc ( r supply) will then turn the ballast on again with the ac input line voltage increasing to the minimum specified value causing vcc to exceed uvlo+. r supply should be set to turn the ballast on at the minimum specified ballast input voltage. the pfc should then be designed such that the dc bus decreases at an input line voltage that is
ir2166 & (pbf) 22 www.irf.com lower than the minimum specified ballast input voltage. this hysteresis will result in clean turn- on and turnoff of the ballast. cs and eol fault mode (fault) should the voltage at the sd/eol pin exceed 3v or decrease below 1v during run mode, the ic enters fault mode and all gate driver outputs, ho, lo and pfc, are latched off in the 'low' state. cph is discharged to com for resetting the preheat time, and ct is discharged to com for disabling the oscillator. to exit fault mode, vcc must be recycled back below the uvlo negative- going turn-off threshold, or, the shutdown pin, sd, must be pulled above 5.2 volts. either of these will force the ic to enter uvlo mode (see state diagram, page 7). once vcc is above the turn- on threshold and sd is below 5.0 volts, the ic will begin oscillating again in the preheat mode. the current sense function will force the ic to enter fault mode only after the voltage at the current sense pin has been pulsed about 25 times with a voltage greater than 1.3 volts during preheat and ignition modes only. these over-currents must occur during the on-time of lo. during run mode, a single pulse on the cs pin above 1.3v will force the ic to enter fault mode. ii. pfc section functional description in most electronic ballasts it is necessary to have the circuit act as a pure resistive load to the ac input line voltage. the degree to which the circuit matches a pure resistor is measured by the phase shift between the input voltage and input current and how well the shape of the input current waveform matches the shape of the sinusoidal input voltage. the cosine of the phase angle between the input voltage and input current is defined as the power factor (pf), and how well the shape of the input current waveform matches the shape of the input voltage is determined by the total harmonic distortion (thd). a power factor of 1.0 (maximum) corresponds to zero phase shift and a thd of 0% represents a pure sinewave (no distortion). for this reason it is desirable to have a high pf and a low thd. to achieve this, the ir2166 includes an active power factor correction (pfc) circuit which, for an ac line input voltage, produces an ac line input current. the control method implemented in the ir2166 is for a boost- type converter (figure 6) running in critical- conduction mode (ccm). this means that during each switching cycle of the pfc mosfet, the circuit waits until the inductor current discharges to zero before turning the pfc mosfet on again. the pfc mosfet is turned on and off at a much higher frequency (>10khz) than the line input frequency (50 to 60hz). lo cs 25 pulses run mode fault mode 2.0v figure 5: fault counter during preheat and ignition cbus + (+) (-) mpfc lpfc dpfc dc bus figure 6: boost-type pfc circuit
ir2166 & (pbf) www.irf.com 23 when the switch mpfc is turned on, the inductor lpfc is connected between the rectified line input (+) and (-) causing the current in lpfc to charge up linearly. when mpfc is turned off, lpfc is connected between the rectified line input (+) and the dc bus capacitor cbus (through diode dpfc) and the stored current in lpfc flows into cbus. as mpfc is turned on and off at a high-frequency, the voltage on cbus charges up to a specified voltage. the feedback loop of the ir2166 regulates this voltage to a fixed value by continuously monitoring the dc voltage and adjusting the on-time of mpfc accordingly. for an increasing dc bus the on- time is decreased, and for a decreasing dc bus the on-time is increased. this negative feedback control is performed with a slow loop speed and a low loop gain such that the average inductor current smoothly follows the low-frequency line input voltage for high power factor and low thd. the on-time of mpfc therefore appears to be fixed (with an additional modulation to be discussed later) over several cycles of the line voltage. with a fixed on-time, and an off-time determined by the inductor current discharging to zero, the result is a system where the switching frequency is free-running and constantly changing from a high frequency near the zero crossing of the ac input line voltage, to a lower frequency at the peaks (figure 7). figure 7: sinusoidal line input voltage (solid line), triangular pfc inductor current and smoothed sinusoidal line input current (dashed line) over one half-cycle of the line input voltage. when the line input voltage is low (near the zero crossing), the inductor current will charge up to a small amount and the discharge time will be fast resulting in a high switching frequency. when the input line voltage is high (near the peak), the inductor current will charge up to a higher amount and the discharge time will be longer giving a lower switching frequency. the triangular pfc inductor current is then smoothed by the emi filter to produce a sinusoidal line input current. the pfc control circuit of the ir2166 (figure 8) only requires four control pins: vbus, comp, zx and pfc. the vbus pin is for sensing the dc bus voltage (via an external resistor voltage divider), the comp pin programs the on-time of mpfc and the speed of the feedback loop, the zx pin detects when the inductor current discharges to zero (via a secondary winding from the pfc inductor), and the pfc pin is the low-side gate driver output for mpfc. v, i t
ir2166 & (pbf) 24 www.irf.com rvbus1 rvbus ccomp lpfc mpfc rpfc dfpc cbus (+) (-) rzx pfc control vbus comp pfc zx com dcomp figure 8:ir2166 simplified pfc control circuit the vbus pin is regulated against a fixed internal 4v reference voltage for regulating the dc bus voltage (figure 9). the feedback loop is performed by an operational transconductance amplifier (ota) that sinks or sources a current to the external capacitor at the comp pin. the resulting voltage on the comp pin sets the threshold for the charging of the internal timing capacitor (c1) and therefore programs the on- time of mpfc. during preheat and ignition modes of the ballast section, the gain of the ota is set to a high level to raise the dc bus level quickly. when the voltage on the v bus pin exceeds 3v, the gain is set to a low level to reduce overshoot. when the voltage on the v bus pin exceeds 4v, the gain is set to a high level again to minimize the transient on the dc bus which can occur during ignition. during run mode, the gain is then decreased to a lower level necessary for achieving high power factor and low thd. figure 9: ir2166 detailed pfc control circuit the off-time of mpfc is determined by the time it takes the lpfc current to discharge to zero. this zero current level is detected by a secondary winding on lpfc which is connected to the zx pin. a positive-going edge exceeding the internal 2v threshold signals the beginning of the off-time. a negative-going edge on the zx pin falling below 1.7v will occur when the lpfc current discharges to zero which signals the end of the off-time and mpfc is turned on again (figure 10). the cycle repeats itself indefinitely until the pfc section is disabled due to a fault detected by the ballast section (fault mode), an over-voltage or under-voltage condition on the dc bus, or, the negative transition of zx pin voltage does not occur. should the negative edge on the zx pin not occur, mpfc will remain off until the watch-dog timer forces a turn-on of mpfc for an on-time duration programmed by the voltage on the comp pin. the watch-dog pulses occur every 400 s indefinitely until a correct positive- and negative- going signal is detected on the zx pin and normal pfc operation is resumed. 7 6 1 q s rq 2.0v vbus comp zx 7.6v 4.0v gain ota1 4.3v 8 pfc q s r2 q r1 comp3 comp4 comp5 rs3 rs4 vcc run mode signal fault mode signal m1 watch dog timer m2 c1 3.0v discharge vcc to uvlo- comp2
ir2166 & (pbf) www.irf.com 25 0 0 0 i lpfc pfc pin zx pin figure 10: lpfc current, pfc pin and zx pin timing diagram. on-time modulation a fixed on-time of mpfc over an entire cycle of the line input voltage produces a peak inductor current which naturally follows the sinusoidal shape of the line input voltage. the smoothed averaged line input current is in phase with the line input voltage for high power factor but the total harmonic distortion (thd), as well as the individual higher harmonics, of the current can still be too high. this is mostly due to cross- over distortion of the line current near the zero- crossings of the line input voltage. to achieve low harmonics which are acceptable to international standard organizations and general market requirements, an additional on-time modulation circuit has been added to the pfc control. this circuit dynamically increases the on-time of mpfc as the line input voltage nears the zero-crossings (figure 11). this causes the peak lpfc current, and therefore the smoothed line input current, to increase slightly higher near the zero-crossings of the line input voltage. this reduces the amount of cross-over distortion in the line input current which reduces the thd and higher harmonics to low levels. 0 0 i lpfc pfc pin near peak region of rectified ac line near zero-crossing regio n of rectified ac line figure 11: on-time modulation near the zero-crossings. over-voltage protection (ovp) should over-voltage occur on the dc bus causing the vbus pin to exceed the internal 4.3v threshold, the pfc output is disabled (set to a logic 'low'). when the dc bus decreases again causing the vbus pin to decrease below the internal 4v threshold, a watch-dog pulse is forced on the pfc pin and normal pfc operation is resumed. under-voltage reset (uvr) when the line input voltage is decreased, interrupted or a brown-out condition occurs, the pfc feedback loop causes the on-time of mpfc
ir2166 & (pbf) 26 www.irf.com to increase in order to keep the dc bus constant. should the on-time increase too far, the resulting peak currents in lpfc can exceed the saturation current limit of lpfc. lpfc will then saturate and very high peak currents and di/dt levels will occur. to prevent this, the maximum on-time is limited by limiting the maximum voltage on the comp pin with an external zener diode dcomp (figure 8). as the line input voltage decreases, the comp pin voltage and therefore the on-time will eventually limit. the pfc can no longer supply enough current to keep the dc bus fixed for the given load power and the dc bus will begin to drop. decreasing the line input voltage further will cause the vbus pin to eventually decrease below the internal 3v threshold (figure 9). when this occurs, vcc is discharged internally to uvlo-, the ir2166 enters uvlo mode and both the pfc and ballast sections are disabled (see state diagram). the start-up supply resistor to vcc, together with the micro- power start-up current of the ir2166, determine the line input turn-on voltage. this should be set such that the ballast turns on at a line voltage level above the under-voltage turn-off level. it is the correct selection of the value of the supply resistor to vcc and the zener diode on the comp pin that correctly program the on and off line input voltage thresholds for the ballast. with these thresholds correctly set, the ballast will turn off due to the 3v under-voltage threshold on the vbus pin, and on again at a higher line input voltage (hysterisis) due to the supply resistor to vcc. this hysterisis will result in a proper reset of the ballast without flickering of the lamp, bouncing of the dc bus or re-ignition of the lamp when the dc bus is too low. pfc over-current protection (optional) in case of fast on/off interruptions of the mains input voltage or during normal lamp ignition, the dc bus voltage level can decrease below the instantaneous rectified line voltage. should this occur, the pfc inductor current and pfc mosfet current can increase to high levels causing the pfc inductor to saturate and/or the pfc mosfet to become damaged. during fast on/off interruptions of the input mains voltage, the dc bus can drop during the time when the mains voltage is interrupted (off). since vcc is still above uvlo-, the ic will continue to operate and will increase the comp pin voltage to increase the pfc mosfet on-time due to the dropping of the dc bus. when the mains voltage returns again quickly, (before vcc reaches uvlo- ), the on-time of the pfc mosfet is too long for the given mains voltage level resulting in high pfc inductor and mosfet currents that can saturate the inductor and/or damage the pfc mosfet (figure 12). figure 12, high pfc inductor current during fast mains on/off (upper trace: dc bus, 100v/div; middle trace: ac line input voltage, 100v/div; lower trace: pfc inductor current 1a/div).
ir2166 & (pbf) www.irf.com 27 during lamp ignition, the dc bus can drop below the rectified ac line voltage causing current to conduct directly from the output of the rectifier, through the pfc inductor and diode, to the dc bus capacitor. this results in a low-frequency offset of current in the pfc inductor. since the zero- crossing detection circuit only detects the high- frequency zero-crossing of the inductor current, the pfc mosfet will turn on again each cycle before the inductor current has reached zero. this causes the pfc to work in a continuous conduction mode and the sum of the low-frequency and high- frequency components of current can saturate the pfc inductor and/or damage the pfc mosfet. to protect against these conditions, a current sense resistor (rs) can be inserted between the source on the pfc mosfet and ground, and a diode (d4) connected from the top of this current- sensing resistor to the vbus pin (figure 13). 13, external over-current protection circuit should high currents occur, the voltage across the current-sensing resistor (rs) will exceed the 4.3v over-voltage protection threshold at the vbus pin and the pfc mosfet will turn off safely limiting the current. the watch-dog timer will then rectified ac line 15 14 13 12 11 ir2166 com vcc vb vs ho 1 2 3 rt cph vbus 4 5 7 rph comp ct 6 7 8 pfc zx 10 cs lo 9 sd/eol 16 rs d4 1n4148 1 ? high current ground device ground restart the pfc as normal (figure 14). the current sensing resistor value should be selected such that the over-current protection does not false trip during normal operation over the entire line voltage range and load range. a current-sensing resistor value, for example, of 1.0 w will set the over- current protection threshold to about 5 a peak. figure 14, pfc inductor current limited using over- current protection circuit (upper trace: dc bus, 100v/div; middle trace: ac line input voltage, 100v/ div; lower trace: pfc inductor current 1a/d iv). the effect that these line and load conditions have on the performance of the ballast depends on the saturation level of the pfc inductor, the selection of the pfc mosfet, the dc bus capacitor value, the maximum on-time limit set by dzcomp, and, how fast vcc decreases below uvlo- when the dc bus drops during ignition (the 3v reset on the vbus pin does not become active until run mode). for these reasons, the ballast designer should perform these mains interrupt and ignition tests carefully to determine the robustness of their final design and to decide if this additional over-current protection circuit is necessary.
ir2166 & (pbf) 28 www.irf.com step 3: program preheat frequency the preheat frequency is programmed with timing resistors rt and rph, and timing capacitor ct. the timing resistors are connected in parallel internally for the duration of the preheat time. the preheat frequency is therefore given as: ? ? ? ? ? ? ? ? + + ? ? ? ? = 1475 51 . 0 2 1 ph t ph t t ph r r r r c f [hertz] (5) or ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 2892 02 . 1 1 2892 02 . 1 1 ph t t t ph t ph f c r r f c r [ohms] (6) step 4: program preheat t ime the preheat time is defined by the time it takes for the capacitor on pin cph to charge up to 10 volts. an internal current source of 3ua flows out of pin cph. the preheat time is therefore given as: 6 33 . 3 e c t ph ph ? = [seconds] (7) or 6 3 . 0 ? ? = e t c ph ph [farads] (8) ballast design equations note: the results from the following design equations can differ slightly from experimental measurements due to ic tolerances, component tolerances, and oscillator over- and undershoot due to internal comparator response time. step 1: program dead-time the dead-time between the gate driver outputs ho and lo is programmed with timing capacitor ct and an internal dead-time resistor rdt. the dead-time is the discharge time of capacitor ct from 3/5vcc to 1/3vcc and is given as: 1475 ? = t dt c t [seconds] (1) or 1475 dt t t c = [farads] (2) step 2: program run frequency the final run frequency is programmed with timing resistor rt and timing capacitor ct. the charge time of capacitor ct from 1/3vcc to 3/5vcc determines the on-time of ho and lo gate driver outputs. the run frequency is therefore given as: ) 1475 51 . 0 ( 2 1 + ? ? = t t run r c f [hertz] (3) or 2892 02 . 1 1 ? ? ? = run t t f c r [ohms] (4)
ir2166 & (pbf) www.irf.com 29 step 5: program maximum ignition current the maximum ignition current is programmed with the external resistor rcs and an internal threshold of 1.3 volts. this threshold determines the over-current limit of the ballast, which can be exceeded when the frequency ramps down towards resonance during ignition and the lamp does not ignite. the maximum ignition current is given as: cs ign r i 3 . 1 = [amps peak] (9) or ign cs i r 3 . 1 = [ohms] (10)
ir2166 & (pbf) 30 www.irf.com pfc design equations step1: calculate pfc inductor value: vbus p f vac vac vbus l out min min min pfc ? ? ? ? ? ? ? = 2 ) 2 ( 2 [henries] (1) where, vbus = dc bus voltage min vac = minim um rms ac input voltage = pfc efficiency (typically 0.95) min f = minim um pfc switching frequency at m inim um ac input voltage out p = ballast output power step 2: calculate peak pfc inductor current: ? ? ? = min out pk vac p i 2 2 [amps peak] (2) note: the pfc inductor m ust not saturate at pk i over the specified ballast operating tem perature range. proper core sizing and air-gapping should be considered in the inductor design. step 3: calculate maximum on-time: ? ? ? = 2 2 min pfc out on vac l p t max [seconds] (3) step 4: calculate m axim um comp voltage: 6 9 . 0 ? = e t v max on max comp [volts] (4) step 5: select zener diode dcomp value: comp d zener voltage max comp v [volts] (5) step 6: calculate resistor rsupply value: iqccuv vac r pk min supply 10 + = [ohms] (6)
ir2166 & (pbf) www.irf.com 31 case outline 16 lead pdip 01-6015 01-3065 00 (ms-001a) 16 lead soic (narrow body) 01-6018 01-3064 00 (ms-012ac)
ir2166 & (pbf) 32 www.irf.com ir world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 data and specifications subject to change without notice. 1/12/2005 leadfree part marking information order information basic part (non-lead free) 16-lead pdip ir2166 order ir2166 16-lead soic ir2166s order ir2166s leadfree part 16-lead pdip ir2166 order ir2166pbf 16-lead soic ir2166s not yet available lead free released non-lead free released part number date code irxxxxxx yww? ?xxxx pin 1 identifier ir logo lot code (prod mode - 4 digit spn code) assembly site code p ? marking code

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